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e see new design recommendations december 1997 order number: 290489-005 n user-selectable 3.3 v or 5 v v cc n user-configurable x8 or x16 operation n 70 ns maximum access time n 28.6 mb/sec burst write transfer rate n 1 million typical erase cycles per block n 56-lead, 1.2 mm x 14 mm x 20 mm tsop package n 56-lead, 1.8 mm x 16 mm x 23.7 mm ssop package n revolutionary architecture ? pipelined command execution ? program during erase ? command superset of intel 28f008sa n 1 ma typical i cc in static mode n 1 a typical deep power-down n 32 independently lockable blocks n state-of-the-art 0.6 m etox? iv flash technology intels 28F016SA 16-mbit flashfile? memory is a revolutionary architecture which is the ideal choice for designing embedded direct-execute code and mass storage data/file flash memory systems. with i nnovative capabilities, low-power, extended temperature operation and high read/program performance, the 28F016SA enables the design of truly mobile, high-performance communications and computing products. the 28F016SA is the highest density, highest performance nonvolatile read/program solution for solid-state storage applications. its symmetrically-blocked architecture (100% compatible with the 28f008sa 8-mbit flashfile memory), extended cycling, extended temperature operation, flexible v cc , fast program and read performance and selective block locking provide highly flexible memory components suitable for resident flash arrays, high-density memory cards and pcmcia-ata flash drives. the 28F016SA dual read voltage enables the design of memory cards which can be interchangeably read/written in 3.3 v and 5.0 v systems. its x8/x16 architecture allows optimization of the memory-to-processor interface. its high read performance and flexible block locking enable both storage and execution of operating systems and application software. manufactured on intels 0.6 m etox iv process technology, the 28F016SA is the most cost-effective, highest density monolithic 3.3 v flashfile memory. new design recommendations: for new 3.3 v v cc designs with this device, intel recommends using 16-mbit word-wide flashfile? memory. reference word-wide flashfile? memory family 28f160s3, 28f320s3 datasheet, order number 290608. for new 3.3 v v cc x8 i/o designs with this device, intel recommends using the 16-mbit byte-wide smart 3 flashfile? memory. reference byte-wide smart 3 flashfile? memory family datasheet, order number 290598. for new 5 v v cc designs with this device, intel recommends using the 16-mbit word-wide flashfile? memory. reference word-wide flashfile? memory family 28f160s5, 28f320s5 datasheet, order number 290609. for new 5 v v cc x8 i/o designs with this device, intel recommends using the 16-mbit byte-wide smart 5 flashfile? memory. reference byte-wide smart 5 flashfile? memory family datasheet, order number 290597. these documents are also available at intels website, http://www.intel.com/design/flcomp. reference only 28F016SA flashfile? memory includes commercial and extended temperature specifications
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28F016SA may contain design defects or errors known as errata. current characterized errata are available upon request. *third-party brands and names are the property of their respective owners. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-9808 or call 1-800-548-4725 or visit intels website at http://www.intel.com copyright ? intel corporation, 1997 cg-041493 *third-party brands and names are the property of their respective owners.
e 28F016SA 3 see new design recommendations contents page page 1.0 introduction .............................................5 1.1 product overview.........................................5 2.0 device pinout .............................................6 2.1 lead descriptions ........................................8 3.0 memory maps ...........................................12 3.1 extended status register memory map .....13 4.0 bus operations, commands and status register definitions .............14 4.1 bus operations for word-wide mode (byte# = v ih ) ...........................................14 4.2 bus operations for byte-wide mode (byte# = v il ) ...........................................14 4.3 28f008sa Ccompatible mode command bus definitions ..........................................15 4.4 28F016SACperformance enhancement command bus definitions.........................16 4.5 compatible status register........................18 4.6 global status register ...............................19 4.7 block status register.................................20 5.0 electrical specifications .................21 5.1 absolute maximum ratings........................21 5.2 capacitance ...............................................22 5.3 timing nomenclature .................................23 5.4 dc characteristics (v cc = 3.3v 10%) .....26 5.5 dc characteristics (v cc = 5.0v 10%, 5.0v 5%) ................29 5.6 ac characteristicsCread only operations ................................................ 32 5.7 power-up and reset timings .................... 37 5.8 ac characteristics for we#Ccontrolled command write operations...................... 38 5.9 ac characteristics for ce#Ccontrolled command write operations...................... 42 5.10 ac characteristics for page buffer write operations ................................................ 46 5.11 erase and word/byte program performance, cycling performance and suspend latency ...................................... 49 6.0 derating curves.................................... 50 7.0 mechanical specifications for tsop ........................................................... 52 8.0 mechanical specifications for ssop ........................................................... 53 9.0 device nomenclature and ordering information ................................................. 54 10.0 additional information .............................. 55
28F016SA e 4 see new design recommendations revision history number description -001 original version -002 added 56-lead ssop package separated ac reading timing specs t avel , t avgl for extended status register reads modified device nomenclature added ordering information added page buffer typical program performance numbers added typical erase suspend latencies for i ccd (deep power-down current) byte# must be at cmos levels added ssop package mechanical specifications revised document status from advanced information to preliminary -003 section 5.11: renamed specification erase suspend latency time to program as auto erase suspend latency time to program section 5.7: added specifications t phel3 , t phel5 tsop dimension a 1 = 0.05 mm (min) ssop dimension b = 0.40 mm (max) minor cosmetic changes -004 update: changed deep power down current changed standby current changed sleep mode current combined commercial and extended temperature information into single datasheet -005 added new design recommendations section to cover page
e 28F016SA 5 see new design recommendations 1.0 introduction the documentation of the intel 28F016SA memory device includes this datasheet, a detailed users manual, and a number of application notes, all of which are referenced at the end of this datasheet. the datasheet is intended to give an overview of the chip feature-set and of the operating ac/dc specifications. the 16-mbit flash product family users manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. it also contains the full list of software algorithm flowcharts, and a brief section on compatibility with intel 28f008sa. 1.1 product overview the 28F016SA is a high-performance 16-mbit (16,777,216 bit) block erasable nonvolatile random access memory organized as either 1 mword x 16 or 2 mbyte x 8. the 28F016SA includes thirty- two 64-kb (65,536) blo cks or thirty-two 32-kw (32,768) blo cks. a chip memory map is shown in figure 4. the implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease-of-use. among the significant enhancements on the 28F016SA: 3.3v low power capability improved program performance dedicated block program/erase protection a 3/5# input pin reconfigures the device internally for optimized 3.3v or 5.0v read/program operation. the 28F016SA will be available in a 56-lead, 1.2 mm thick, 14 mm x 20 mm tsop type i package or a 56-lead, 1.8 mm thick, 16 mm x 23.7 mm ssop package. the tsop form factor and pinout allow for very high board layout densities. ssop packaging provides relaxed lead spacing dimensions. a command user interface (cui) serves as the system interface betw een the microprocessor or microcontroller and the internal memory operation. internal algorithm automation allows word/byte programs and block erase operations to be executed using a two-write command sequence to the cui in the same way as the 28f008sa 8-mbit flashfile memory. a superset of commands have been added to the basic 28f008sa command-set to achieve higher program performance and provide additional capabilities. these new commands and features include: page buffer writes to flash command queueing capability automatic data programs during erase software locking of memory blocks two-byte successive programs in 8-bit systems erase all unlocked blocks writing of memory data is performed in either byte or word increments typically within 6 s, a 33% improvement over the 28f008sa. a block erase operation erases one of the 32 blo cks in typically 0.6 sec, independent of the other blo cks, which is a 65% improvement over the 28f008sa. each block can be written and erased a minimum of 100,000 cycles. systems can achieve typically one- million block erase cycles by providing wear-leveling algorithms and graceful block retirement. these techniques have already been employed in many flash file systems. additi onally, wear leveling of block erase cycles can be used to minimize the program/erase performance differences across blocks. the 28F016SA incorporates two page buffers of 256 bytes (128 words) each to allow page data writes. this feature can improve a system write performance by up to 4.8 times over previous flash memory devices. all operations are started by a sequence of command writes to the device. three status registers (described in detail later) and a ry/by# output pin provide information on the progress of the requested operation. while the 28f008sa requires an operation to complete before the next operation can be requested, the 28F016SA allows queueing of the next operation while the memory executes the current operation. this eliminates system over head
28F016SA e 6 see new design recommendations when writing several bytes in a row to the array or erasing several blocks at the same time. the 28F016SA can also perform program operations to one block of memory while performing erase of another block. the 28F016SA provides user-selectable block locking to protect code or data such as device drivers, pcmcia card information, rom-executable o/s or application code. each block has an associated nonvolatile lock-bit which determines the lock status of the block. in addition, the 28F016SA has a master write protect pin (wp#) which prevents any modifications to memory blocks whose lock-bits are set. the 28F016SA contains three types of status registers to accomplish various functions: a compatible status register (csr) which is 100% compatible with the 28f008sa flashfile memorys status register. this register, when used alone, provides a straightforward upgrade capability to the 28F016SA from a 28f008sa- based design. a global status register (gsr) which informs the system of comm and queue status, page buffer status, and overall write state machine (wsm) status. 32 block status registers (bsrs) which provide block-specific status information such as the block lock-bit status. the gsr and bsr memory maps for byte-wide and word-wide modes are shown in figures 5 and 6. the 28F016SA incorporates an open drain ry/by# output pin. this feature allows the user to or-tie many ry/by# pins together in a multiple memory configuration such as a resident flash array. other configurations of the ry/by# pin are enabled via special cui commands and are described in detail in the 16-mbit flash product family users manual. the 28F016SA also incorporates a dual chip-enable function with two input pins, ce 0 # and ce 1 #. these pins have exactly the same functionality as the regular chip-enable pin ce# on the 28f008sa. for minimum chip designs, ce 1 # may be tied to ground to use ce 0 # as the chip enable input. the 28F016SA uses the logical combination of these two signals to enable or disable the entire chip. both ce 0 # and ce 1 # must be active low to enable the device and, if either one becomes inactive, the chip will be disabled. this feature, along with the open drain ry/by# pin, allows the system desi gner to reduce the number of control pins used in a large array of 16-mbit devices. the byte# pin allows either x8 or x16 read/programs to the 28F016SA. byte# at logic low selects 8-bit mode with address a 0 selecting between low byte and high byte. on the other hand, byte# at logic high enables 16-bit operation with address a 1 becoming the lowest order address and address a 0 is not used (dont care). a device block diagram is shown in figure 1. the 28F016SA is specified for a maximum access time of 70 ns (t acc ) at 5.0v operation (4.75v to 5.25v) over the commercial temperature range (0 c to +70 c). a corresponding maximum access time of 120 ns at 3.3v (3.0v to 3.6v and 0 c to +70 c) is achieved for reduced power consumption applications. the 28F016SA incorporates an automatic power saving (aps) feature which substantially reduces the active current when the device is in the static mode of operation (addresses not switching). in aps mode, the typical i cc current is 1 ma at 5.0v (0.8 ma at 3.3v). a deep power-down mode of operation is invoked when the rp# (called pwd# on the 28f008sa) pin transitions low. this mode brings the device power consumption to less than 1.0 a, typically, and provides additional write protection by acting as a device reset pin during power transitions. a reset time is required from rp# switching high until outputs are again valid. in the deep power-down state, the wsm is reset (any current operation will abort) and the csr, gsr and bsr registers are cleared. a cmos standby mode of operation is enabled when either ce 0 # or ce 1 # transitions high and rp# stays high with all input control pins at cmos levels. in this mode, the device typically draws an i cc standby current of 50 a. 2.0 device pinout the 28F016SA 56-lead tsop type i pinout configuration is shown in figure 2. the 56-lead ssop pinout configuration is shown in figure 3.
e 28F016SA 7 see new design recommendations output buffer output buffer input buffer input buffer i/o logic id register csr data comparator y decoder x decoder 64-kbyte block 0 64-kbyte block 1 64-kbyte block 30 64-kbyte block 31 program/erase voltage switch address counter input buffer y gating/sensing output multiplexer gnd dq 8-15 dq 0-7 3/5# byte# ce0# ce1# oe# we# wp# rp# v cc 3/5# ry/by# v pp a 0-20 address queue latches cui data queue registers page buffers wsm esrs 0489_01 figure 1. 28F016SA block diagram architectural evolution includes page buffers, queue registers and extended status registers
28F016SA e 8 see new design recommendations 2.1 lead descriptions symbol type name and function a 0 input byte-select address: selects between high and low byte when the device is in x8 mode. this address is latched in x8 data programs. not used in x16 mode (i.e., the a 0 input buffer is turned off when byte# is high). a 1 C a 15 input word-select addresses: select a word within one 64-kbyte block. a 6 C15 selects 1 of 1024 rows, and a 1 C5 selects 16 of 512 columns. these addresses are latched during data programs. a 16 C a 20 input block-select addresses: select 1 of 32 erase blocks. these addresses are latched during data programs, block erase and lock block operations. dq 0 C dq 7 input/output low-byte data bus: inputs data and commands during cui write cycles. outputs array, buffer, identifier or status data in the appropriate read mode. floated when the chip is deselected or the outputs are disabled. dq 8 C dq 15 input/output high-byte data bus: inputs data during x16 data program operations. outputs array, buffer or identifier data in the appropriate read mode; not used for status register reads. floated when the chip is deselected or the outputs are disabled. ce 0 #,ce 1 # input chip enable inputs : activate the devices control logic, input buffers, decoders and sense amplifiers. with either ce 0 # or ce 1 # high, the device is deselected and power consumption reduces to standby levels upon completion of any current data program or block erase operations. both ce 0 #, ce 1 # must be low to select the device. all timing specifications are the same for both signals. device selection occurs with the latter falling edge of ce 0 # or ce 1 #. the first rising edge of ce 0 # or ce 1 # disables the device. rp# input reset/power-down: rp# low places the device in a deep power- down state. all circuits that burn static power, even those circuits enabled in standby mode, are turned off. when returning from deep power-down, a recovery time is required to allow these circuits to power-up. when rp# goes low, any current or pending wsm operation(s) are terminated, and the device is reset. all status registers return to ready (with all status flags cleared). oe# input output enable: gates device data through the output buffers when low. the outputs float to tri-state off when oe# is high. note: ce x # overrides oe#, and oe# overrides we#. we# input write enable: controls access to the cui, page buffers, data queue registers and address queue latches. we# is active low, and latches both address and data (command or array) on its rising edge. page buffer addresses are latched on the falling edge of we#.
e 28F016SA 9 see new design recommendations 2.1 lead descriptions (continued) symbol type name and function ry/by# open drain output ready/busy: indicates status of the internal wsm. when low, it indicates that the wsm is busy performing an operation. ry/by# high indicates that the wsm is ready for new operations (or wsm has completed all pending operations), or block erase is suspended, or the device is in deep power-down mode. this output is always active (i.e., not floated to tri-state off when oe# or ce 0 #,ce 1 # are high), except if a ry/by# pin disable command is issued. wp# input write protect: erase blocks can be locked by writing a nonvolatile lock-bit for each block. when wp# is low, those locked blocks as reflected by the block-lock status bits (bsr.6), are protected from inadvertent data programs or block erases. when wp# is high, all blocks can be written or erased regardless of the state of the lock-bits. the wp# input buffer is disabled when rp# transitions low (deep power-down mode). byte# input byte enable: byte# low places device in x8 mode. all data is then input or output on dq 0 C7 , and dq 8 C15 float. address a 0 selects between the high and low byte. byte# high places the device in x16 mode, and turns off the a 0 input buffer. address a 1 then becomes the lowest order address. 3/5# input 3.3/5.0 volt select: 3/5# high configures internal circuits for 3.3v operation. 3/5# low configures internal circuits for 5.0v operation. notes: reading the array with 3/5# high in a 5.0v system could damage the device. there is a significant delay from 3/5# switching to valid data. v pp supply erase/program power supply: for erasing memory array blocks or writing words/bytes/pages into the flash array. v cc supply device power supply (3.3v 10%, 5.0v 10%, 5.0v 5%): do not leave any power pins floating. gnd supply ground for all internal circuitry: do not leave any ground pins floating. nc no connect: lead may be driven or left floating.
28F016SA e 10 see new design recommendations 29 30 31 32 33 34 56 55 53 54 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 e28F016SA 56-lead tsop pinout 1.2 mm x 14 mm x 20 mm top view 28f032sa 28f016sv 28f032sa 28f016sv 3/5# rp# gnd ce # 2 ce # 1 a 20 a 19 a 18 a 17 a 16 v cc a 15 a 14 a 13 a 12 ce # 0 v pp a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 wp# we# oe# ry/by# gnd gnd byte# nc nc dq 9 dq 1 dq 8 dq 0 v cc wp# we# oe# ry/by# gnd gnd byte# nc nc dq 9 dq 1 dq 8 dq 0 v cc wp# we# oe# ry/by# gnd gnd byte# nc nc dq 9 dq 1 dq 8 dq 0 v cc a 0 a 0 a 0 dq 2 dq 2 dq 2 dq 10 dq 10 dq 10 dq 3 dq 3 dq 3 dq 11 dq 11 dq 11 v cc v cc v cc dq 4 dq 4 dq 4 dq 12 dq 12 dq 12 dq 5 dq 5 dq 5 dq 13 dq 13 dq 13 dq 6 dq 6 dq 6 dq 14 dq 14 dq 14 dq 7 dq 7 dq 7 dq 15 dq 15 dq 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 3/5# rp# gnd ce # 1 a 20 a 19 a 18 a 17 a 16 v cc a 15 a 14 a 13 a 12 ce # 0 v pp a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 nc 3/5# rp# gnd ce # 1 a 20 a 19 a 18 a 17 a 16 v cc a 15 a 14 a 13 a 12 ce # 0 v pp a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 nc nc nc 0489_02 note: 56-lead tsop mechanical diagrams and dimensions are shown at the end of this specification. figure 2. tsop pinout configuration
e 28F016SA 11 see new design recommendations da28F016SA 56-lead ssop standard pinout 1.8 mm x 16 mm x 23.7 mm top view 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 28f016sv rp# gnd byte# nc nc gnd v pp a 11 a 10 a 9 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 v cc dq 9 dq 1 dq 8 dq 0 a 0 dq 2 dq 10 dq 3 dq 11 rp# gnd byte# nc nc gnd v pp a 11 a 10 a 9 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 v cc dq 9 dq 1 dq 8 dq 0 a 0 dq 2 dq 10 dq 3 dq 11 28f016sv ry/by# nc we# wp# oe# gnd ce # 0 a 12 a 13 a 14 a 15 ce # 1 a 20 a 19 a 18 a 17 a 16 v cc dq 6 dq 14 dq 7 dq 15 dq 13 dq 5 dq 12 dq 4 v cc ry/by# 3/5# nc we# wp# oe# gnd ce # 0 a 12 a 13 a 14 a 15 ce # 1 a 20 a 19 a 18 a 17 a 16 v cc dq 6 dq 14 dq 7 dq 15 dq 13 dq 5 dq 12 dq 4 v cc 3/5# 0489_17 figure 3. ssop pinout configuration
28F016SA e 12 see new design recommendations 3.0 memory maps 64-kbyte block 1fffff 31 1f0000 1effff 1e0000 1dffff 1d0000 1cffff 1c0000 1bffff 30 29 28 27 1b0000 1affff 1a0000 19ffff 190000 18ffff 180000 17ffff 26 25 24 23 170000 16ffff 160000 15ffff 150000 14ffff 140000 13ffff 22 21 20 19 130000 12ffff 120000 11ffff 110000 10ffff 100000 0fffff 18 17 16 15 0f0000 0effff 0e0000 0dffff 0d0000 0cffff 0c0000 0bffff 14 13 12 11 0b0000 0affff 0a0000 09ffff 090000 08ffff 080000 07ffff 10 9 8 7 070000 06ffff 060000 05ffff 050000 04ffff 040000 03ffff 6 5 4 3 030000 02ffff 020000 01ffff 010000 00ffff 000000 2 1 0 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block a [20-0] 0489_03 figure 4. 28F016SA memory map (byte-wide mode)
e 28F016SA 13 see new design recommendations 3.1 extended status register memory map x8 mode a[20-0] . . . 1f0004h 1f0003h 1f0002h 1f0000h 1f0001h 1f0005h 1f0006h 000004h 000003h 000002h 000000h 000001h 000006h 000005h 010002h reserved gsr reserved bsr 0 reserved reserved reserved reserved gsr reserved bsr 31 reserved reserved 0489_04 figure 5. extended status register memory map (byte-wide mode) x16 mode a[20-1] . . . 00002h 00000h 00001h 00003h 08001h reserved gsr reserved bsr 0 reserved reserved reserved f8002h f8000h f8001h f8003h reserved gsr reserved bsr 31 reserved reserved 0489_05 figure 6. extended status register memory map (word-wide mode)
28F016SA e 14 see new design recommendations 4.0 bus operations, commands and status register definitions 4.1 bus operations for word-wide mode (byte# = v ih ) mode notes rp# ce 1 #ce 0 # oe# we# a 1 dq 0 C15 ry/by# read 1,2,7 v ih v il v il v il v ih xd out x output disable 1,6,7 v ih v il v il v ih v ih x high z x standby 1,6,7 v ih v il v ih v ih v ih v il v ih x x x high z x deep power-down 1,3 v il xxxxx high z v oh manufacturer id 4 v ih v il v il v il v ih v il 0089h v oh device id 4 v ih v il v il v il v ih v ih 66a0h v oh write 1,5,6 v ih v il v il v ih v il xd in x 4.2 bus operations for byte-wide mode (byte# = v il ) mode notes rp# ce 1 #ce 0 # oe# we# a 0 dq 0C7 ry/by# read 1,2,7 v ih v il v il v il v ih xd out x output disable 1,6,7 v ih v il v il v ih v ih x high z x standby 1,6,7 v ih v il v ih v ih v ih v il v ih x x x high z x deep power-down 1,3 v il xxxxx high z v oh manufacturer id 4 v ih v il v il v il v ih v il 89h v oh device id 4 v ih v il v il v il v ih v ih a0h v oh write 1,5,6 v ih v il v il v ih v il xd in x notes: 1. x can be v ih or v il for address or control pins except for ry/by#, which is either v ol or v oh . 2. ry/by# output is open drain. when the wsm is ready, block erase is suspended or the device is in deep power-down mode. ry/by# will be at v oh if it is tied to v cc through a resistor. ry/by# at v oh is independent of oe# while a wsm operation is in progress. 3. rp# at gnd 0.2v ensures the lowest deep power-down current. 4. a 0 and a 1 at v il provide manufacturer id codes in x8 and x16 modes, respectively. a 0 and a 1 at v ih provide device id codes in x8 and x16 modes, respectively. all other addresses are set to zero. 5. commands for different block erase operations, data program operations or lock-block operations can only be successfully completed when v pp = v pph . 6. while the wsm is running, ry/by# in level-mode (default) stays at v ol until all operations are complete. ry/by# goes to v oh when the wsm is not busy or in erase suspend mode. 7. ry/by# may be at v ol while the wsm is busy performing various operations; for example, a status register read during a data program operation.
e 28F016SA 15 see new design recommendations 4.3 28f008sa Ccompatible mode command bus definitions first bus cycle second bus cycle command notes oper addr data (4) oper addr data read array write x xxffh read aa ad intelligent identifier 1 write x xx90h read ia id read compatible status register 2 write x xx70h read x csrd clear status register 3 write x xx50h word/byte program write x xx40h write pa pd alternate word/byte program write x xx10h write pa pd block erase/confirm write x xx20h write ba xxd0h erase suspend/resume write x xxb0h write x xxd0h address data a = array address ad = array data ba = block address csrd = csr data ia = identifier address id = identifier data pa = program address pd = program data x = dont care notes: 1. following the intelligent identifier command, two read operations access the manufacturer and device signature code s. 2. the csr is automatically available after device enters data program, block erase, or suspend operations. 3. clears csr.3, csr.4 and csr.5. also clears gsr.5 and all bsr.5 and bsr.2 bits. 4. the upper byte of the data bus (dq 8 C15 ) during command writes is a dont care in x16 operation of the device. see status register definitions.
28F016SA e 16 see new design recommendations 4.4 28F016SA Cperformance enhancement command bus definitions first bus cycle second bus cycle third bus cycle command mode notes oper addr data (12) oper addr data (12) oper addr data read extended status register 1 write x xx71h read ra gsrd bsrd page buffer swap 7 write x xx72h read page buffer write x xx75h read pba pd single load to page buffer write x xx74h write pba pd sequential load to page buffer x8 4,6,10 write x xxe0h write x bcl write x bch x16 4,5,6,10 write x xxe0h write x wcl write x wch page buffer write to flash x8 3,4,9,10 write x xx0ch write a 0 bc(l,h) write pa bc(h,l) x16 4,5,10 write x xx0ch write x wcl write pa wch two-byte program x8 3 write x xxfbh write a 0 wd(l,h) write pa wd(h,l) lock block/confirm write x xx77h write ba xxd0h upload status bits/confirm 2 write x xx97h write x xxd0h upload device information write x xx99h write x xxd0h erase all unlocked blocks/confirm write x xxa7h write x xxd0h ry/by# enable to level-mode 8 write x xx96h write x xx01h ry/by# pulse-on- write 8 write x xx96h write x xx02h ry/by# pulse-on- erase 8 write x xx96h write x xx03h ry/by# disable 8 write x xx96h write x xx04h sleep 11 write x xxf0h abort write x xx80h address data ba = block address ad = array data wc (l,h) = word count (low, high) pba = page buffer address pd = page buffer data bc (l,h) = byte count (low, high) ra = extended register address bsrd = bsr data wd (l,h) = write data (low, high) pa = program address gsrd = gsr data x = dont care
e 28F016SA 17 see new design recommendations notes: 1. ra can be the gsr address or any bsr address. see figures 5 and 6 for extended status register memory maps. 2. upon device power-up, all bsr lock-bits come up locked. the upload status bits command must be written to reflect the actual lock-bit status. 3. a 0 is automatically complemented to load the second byte of data. byte# must be at v il . the a 0 value determines which wd/bc is supplied first: a 0 = 0 looks at the wdl/bcl, a 0 = 1 looks at the wdh/bch. 4. bch/wch must be at 00h for this product because of the 256-byte (128-word) page buffer size and to avoid writing the page buffer contents into more than one 256-byte segment within an array block. they are simply shown for future page buffer expandability. 5. in x16 mode, only the lower byte dq 0 C7 is used for wcl and wch. the upper byte dq 8C15 is a dont care. 6. pba and pd (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown. 7. this command allows the user to swap between available page buffers (0 or 1). 8. these commands reconfigure the ry/by# output to one of two pulse-modes or enable and disable the ry/ by# function. 9. program address, pa, is the destination address in the flash array which must match the source address in the page buffer. refer to the 16-mbit flash product family users manual . 10. bcl = 00h corresponds to a byte count of 1. similarly, wcl = 00h corresponds to a word count of 1. 11. to ensure that the 28F016SAs power consumption during sleep mode reaches the deep power-down current level, the system also needs to de-select the chip by taking either or both ce 0 # or ce 1 # high. 12. the upper byte of the data bus (dq 8 C15 ) during command writes is a dont care in x16 operation of the device.
28F016SA e 18 see new design recommendations 4.5 compatible status register wsms ess es dws vpps r r r 76543210 notes: csr.7 = write state machine status 1 = ready 0 = busy ry/by# output or wsms bit must be checked to determine completion of an operation (erase suspend, block erase or data program) before the appropriate status bit (ess, es or dws) is checked for success. csr.6 = erase-suspend status 1 = erase suspended 0 = erase in progress/completed csr.5 = erase status 1 = error in block erasure 0 = successful block erase if dws and es are set to 1 during a block erase attempt, an improper command sequence was entered. clear the csr and attempt the operation again. csr.4 = data write status 1 = error in data program 0 = data program successful csr.3 = v pp status 1 = v pp low detect, operation abort 0 = v pp ok the vpps bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm interrogates v pp s level only after the data program or block erase command sequences have been entered, and informs the system if v pp has not been switched on. vpps is not guaranteed to report accurate feedback between v ppl and v pph . csr.2C0 = reserved for future enhancements these bits are reserved for future use; mask them out when polling the csr.
e 28F016SA 19 see new design recommendations 4.6 global status register wsms oss dos dss qs pbas pbs pbss 76543210 notes: gsr.7 = write state machine status 1 = ready 0 = busy [1] ry/by# output or wsms bit must be checked to determine completion of an operation (block lock, erase suspend, any ry/by# reconfig- uration, upload status bits, block erase or data program) before the appropriate status bit (oss or dos) is checked for success. gsr.6 = operation suspend status 1 = operation suspended 0 = operation in progress/completed gsr.5 = device operation status 1 = operation unsuccessful 0 = operation successful or currently running gsr.4 = device sleep status 1 = device in sleep 0 = device not in sleep matrix 5/4 0 0 = operation successful or currently running 0 1 = device in sleep mode or pending sleep 1 0 = operation unsuccessful 1 1 = operation unsuccessful or aborted if operation currently running, then gsr.7 = 0. if device pending sleep, then gsr.7 = 0. operation aborted: unsuccessful due to abort command. gsr.3 = queue status 1 = queue full 0 = queue available gsr.2 = page buffer available status 1 = one or two page buffers available 0 = no page buffer available the device contains two page buffers. gsr.1 = page buffer status 1 = selected page buffer ready 0 = selected page buffer busy selected page buffer is currently busy with wsm operation. gsr.0 = page buffer select status 1 = page buffer 1 selected 0 = page buffer 0 selected note: 1. when multiple operations are queued, checking bsr.7 only provides indication of completion for that particular block. gsr.7 provides indication when all queued operations are completed.
28F016SA e 20 see new design recommendations 4.7 block status register bs bls bos boas qs vpps r r 76543210 notes: bsr.7 = block status 1 = ready 0 = busy [1] ry/by# output or bs bit must be checked to determine completion of an operation (block lock, erase suspend, any ry/by# reconfiguration, upload status bits, block erase or data program) before the appropriate status bits (bos, bls) is checked for success. bsr.6 = block-lock status 1 = block unlocked for program/erase 0 = block locked for program/erase bsr.5 = block operation status 1 = operation unsuccessful 0 = operation successful or currently running the boas bit will not be set until bsr.7 = 1. bsr.4 = block operation abort status 1 = operation aborted 0 = operation not aborted matrix 5/4 0 0 = operation successful or currently running 0 1 = not a valid combination 1 0 = operation unsuccessful 1 1 = operation aborted operation halted via abort command. bsr.3 = queue status 1 = queue full 0 = queue available bsr.2 = v pp status 1 = v pp low detect, operation abort 0 = v pp ok bsr.1 C0 = reserved for future enhancements these bits are reserved for future use; mask them out when polling the bsrs. note: 1. when multiple operations are queued, checking bsr.7 only provides indication of completion for that particular block. gsr.7 provides indication when all queued operations are completed.
e 28F016SA 21 see new design recommendations 5.0 electrical specifications 5.1 absolute maximum ratings* temperature under bias .................... 0c to +80c storage temperature................... C65c to +125c notice: this is a production datasheet. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. v cc = 3.3v 10% systems sym parameter notes min max units test conditions t a operating temperature, commercial 1 0 70 c ambient temperature v cc v cc with respect to gnd 2 C0.2 7.0 v v pp v pp supply voltage with respect to gnd 2,3 C0.2 14.0 v v voltage on any pin (except v cc , v pp ) with respect to gnd 2 C0.5 v cc +0.5 v i current into any non-supply pin 5 30 ma i out output short circuit current 4 100 ma v cc = 5.0v 10% , v cc = 5.0v 5% systems (6) sym parameter notes min max units test conditions t a operating temperature, commercial 1 0 70 c ambient temperature v cc v cc with respect to gnd 2 C0.2 7.0 v v pp v pp supply voltage with respect to gnd 2,3 C0.2 14.0 v v voltage on any pin (except v cc , v pp ) with respect to gnd 2 C2.0 7.0 v i current into any non-supply pin 5 30 ma i out output short circuit current 4 100 ma notes: 1. operating temperature is for commercial product defined by this specification. 2. minimum dc voltage is C 10% on input/output pins. during transitions, this level may undershoot to C2.0v for periods <20 ns. maximum dc voltage on input/output pins is v cc + 10% which, during transitions, may overshoot to v cc + 2.0v for periods <20 ns. 3. maximum dc voltage on v pp may overshoot to +14.0v for periods <20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. 5. this specification also applies to pins marked nc. 6. 5% v cc specifications refer to the 28F016SA-070 in its high speed test configuration.
28F016SA e 22 see new design recommendations 5.2 capacitance for a 3.3v system: symbol parameter notes typ max units test conditions c in capacitance looking into an address/control pin 1 68pft a = +25 c, f = 1.0 mhz c out capacitance looking into an output pin 1 8 12 pf t a = +25 c, f = 1.0 mhz c load load capacitance driven by outputs for timing specifications 1 50 pf for v cc = 3.3v 10% equivalent testing load circuit 2.5 ns 50 w transmission line delay for a 5.0v system: symbol parameter notes typ max units test conditions c in capacitance looking into an address/control pin 1 68pft a = +25 c, f = 1.0 mhz c out capacitance looking into an output pin 1 8 12 pf t a = +25 c, f = 1.0 mhz c load load capacitance driven by outputs for timing specifications 1 100 pf for v cc = 5.0v 10% 30 pf for v cc = 5.0v 5% equivalent testing load circuit for v cc 10% 2.5 ns 25 w transmission line delay equivalent testing load circuit for v cc 5% 2.5 ns 83 w transmission line delay note: 1. sampled, not 100% tested.
e 28F016SA 23 see new design recommendations 5.3 timing nomenclature all 3.3v system timings are measured from where signals cross 1.5v. for 5.0v systems use the standard jedec cross point definitions. each timing parameter consists of five characters. some common examples are defined below: t ce t elqv time(t) from ce# (e) going low (l) to the outputs (q) becoming valid (v) t oe t glqv time(t) from oe# (g) going low (l) to the outputs (q) becoming valid (v) t acc t avqv time(t) from address (a) valid (v) to the outputs (q) becoming valid (v) t as t avwh time(t) from address (a) valid (v) to we# (w) going high (h) t dh t whdx time(t) from we# (w) going high (h) to when the data (d) can become undefined (x) pin characters pin states a address inputs h high d data inputs l low q data outputs v valid e ce# (chip enable) x driven, but not necessarily valid f byte# (byte enable) z high impedance g oe# (output enable) w we# (write enable) p rp# (deep power-down pin) r ry/by# (ready busy) v any voltage level y 3/5# pin 5v v cc at 4.5v minimum 3v v cc at 3.0v minimum
28F016SA e 24 see new design recommendations test points input output 2.0 0.8 0.8 2.0 2.4 0.45 0489_06 ac test inputs are driven at v oh (2.4 vttl) for a logic 1 and v ol (0.45 vttl) for a logic 0. input timing begins at v ih (2.0 vttl) and v il (0.8 vttl). output timing ends at v ih and v il . input rise and fall times (10% to 90%) <10 ns. figure 7. transient input/output reference waveform (v cc = 5.0v 10%) for standard test configuration (1) test points input output 1.5 3.0 0.0 1.5 0489_07 ac test inputs are driven at 3.0v for a logic 1 and 0.0v for a logic 0. input timing begins, and output timing ends, at 1.5v. input rise and fall times (10% to 90%) <10 ns. figure 8. transient input/output reference waveform (v cc = 3.3v 10% ) high speed reference waveform (2) (v cc = 5.0v 5%) notes: 1. testing characteristics for 28F016SA-080/28F016SA-100. 2. testing characteristics for 28F016SA-070/28F016SA-120/28F016SA-150.
e 28F016SA 25 see new design recommendations from output under test test point total capacitance = 100 pf 2.5 ns of 25 transmission line w 0489_08 figure 9. transient equivalent testing load circuit (v cc = 5.0v 10%) from output under test test point total capacitance = 50 pf 2.5 ns of 50 transmission line w 0489_09 figure 10. transient equivalent testing load circuit (v cc = 3.3v 10% ) from output under test test point total capacitance = 30 pf 2.5 ns of 83 transmission line w 0489_10 figure 11. high speed transient equivalent testing load circuit (v cc = 5.0v 5%)
28F016SA e 26 see new design recommendations 5.4 dc characteristics: commercial and extended temperature v cc = 3.3v 10%, t a = 0 c to +70 c, C40 c to +85 c 3/5# = pin set high for 3.3v operations temp comm extended sym parameter notes typ max typ max units test conditions i il input load current 1 1 1 a v cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 10 a v cc = v cc max v in = v cc or gnd i ccs v cc standby current 1,5,6 50 100 70 250 a v cc = v cc max ce 0 #, ce 1 #, rp#, = v cc 0.2v byte#, wp#, 3/5# = v cc 0.2v or gnd 0.2v 14110ma v cc = v cc max ce 0 #, ce 1 #, rp# = v ih byte#, wp#, 3/5# = v ih or v il i ccd v cc deep power- down current 115 335 a rp# = gnd 0.2v byte# = gnd 0.2v or v cc 0.2v i ccr 1v cc read current 1,4,5 30 35 30 40 ma v cc = v cc max cmos: ce 0 #, ce 1 # = gnd 0.2v, byte# = gnd 0.2v or v cc 0.2v, inputs = gnd 0.2v or v cc 0.2v ttl: ce 0 #, ce 1 # = v il , byte# = v il or v ih , inputs = v il or v ih f = 8 mhz, i out = 0 ma i ccr 2v cc read current 1,4,5 15 20 15 25 ma v cc = v cc max cmos: ce 0 #, ce 1 # = gnd 0.2v, byte# = gnd 0.2v or v cc 0.2v, inputs = gnd 0.2v or v cc 0.2v ttl: ce 0 #, ce 1 # = v il , byte# = v il or v ih , inputs = v il or v ih f = 4 mhz, i out = 0 ma i ccw v cc program current for word or byte 1 8 12 8 12 ma program in progress i cce v cc block erase current 1 6 12 6 12 ma block erase in progress i cces v cc erase suspend current 1,2 3 6 3 6 ma ce 0 #, ce 1 # = v ih block erase suspended
e 28F016SA 27 see new design recommendations 5.4 dc characteristics: commercial and extended temperature (continued) v cc = 3.3v 10%, t a = 0 c to +70 c, C40 c to +85 c 3/5# = pin set high for 3.3v operations temp comm extended sym parameter notes typ max typ max units test conditions i pps v pp standby/ 1 1 10 1 10 a v pp v cc i ppr read current 65 200 65 200 a v pp > v cc i ppd v pp deep power- down current 1 0.2 5 0.2 5 a rp# = gnd 0.2v
28F016SA e 28 see new design recommendations 5.4 dc characteristics: commercial and extended temperature (continued) v cc = 3.3v 10%, t a = 0 c to +70 c, C40 c to +85 c 3/5# = pin set high for 3.3v operations temp comm/extended sym parameter notes min typ max units test conditions i ppw v pp program current for word or byte 11015ma v pp = v pph program in progress i ppe v pp block erase current 1 4 10 ma v pp = v pph block erase in progress i ppes v pp erase suspend current 1 65 200 a v pp = v pph block erase suspended v il input low voltage C0.3 0.8 v v ih input high voltage 2.0 v cc + 0.3 v v ol output low voltage 0.4 v v cc = v cc min i ol = 4 ma v oh1 output high voltage 2.4 v v cc = v cc min i oh = C2.0 ma v oh2 v cc C0.2 v v cc = v cc min i oh = C100 a v ppl v pp during normal operations 3 0.0 6.5 v v pph v pp during program/ erase operations 3 11.4 12.0 12.6 v v lko v cc program/erase lock voltage 2.0 v notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 3.3v, v pp = 12.0v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. i cces is specified with the device deselected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. block erases, word/byte programs and lock block operations are inhibited when v pp = v ppl and not guaranteed in the range between v pph and v ppl . 4. automatic power savings (aps) reduces i ccr to less than 1 ma in static operation. 5. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 6. standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer. default the device into read array or read status register mode before entering standby to ensure standby current levels.
e 28F016SA 29 see new design recommendations 5.5 dc characteristics: commercial and extended temperature v cc = 5.0v 10%, 5.0v 5%, t a = 0 c to +70 c, C40 c to +85 c 3/5# pin set low for 5v operations temp comm extended sym parameter notes typ max typ max units test conditions i il input load current 1 1 1 a v cc = v cc max v in = v cc or gnd i lo output leakage current 1 10 10 a v cc = v cc max v in = v cc or gnd i ccs v cc standby current 1,5,6 50 100 70 250 a v cc = v cc max ce 0 #, ce 1 #, rp# = v cc 0.2v byte#, wp#, 3/5# = v cc 0.2v or gnd 0.2v 24210ma v cc = v cc max ce 0 #, ce 1 #, rp# = v ih byte#, wp#, 3/5# = v ih or v il i ccd v cc deep power- down current 1151060a rp# = gnd 0.2v byte# = gnd 0.2v or v cc 0.2v i ccr 1v cc read current 1,4,5 50 60 55 70 ma v cc = v cc max cmos: ce 0 #, ce 1 # = gnd 0.2v, byte# = gnd 0.2v or v cc 0.2v, inputs = gnd 0.2v or v cc 0.2v ttl: ce 0 #, ce 1 # = v il , byte# = v il or v ih , inputs = v il or v ih f = 10 mhz, i out = 0 ma i ccr 2v cc read current 1,4,5 30 35 30 35 ma v cc = v cc max cmos: ce 0 #, ce 1 # = gnd 0.2v, byte# = gnd 0.2v or v cc 0.2v, inputs = gnd 0.2v or v cc 0.2v ttl: ce 0 #, ce 1 # = v il , byte# = v il or v ih , inputs = v il or v ih f = 5 mhz, i out = 0 ma i ccw v cc program current for word or byte 1 25 35 25 35 ma program in progress i cce v cc block erase current 1 18 25 18 25 ma block erase in progress i cces v cc erase suspend current 1,2 5 10 5 10 ma ce 0 #, ce 1 # = v ih block erase suspended
28F016SA e 30 see new design recommendations 5.5 dc characteristics: commercial and extended temperature (continued) v cc = 5.0v 10%, 5.0v 5%, t a = 0 c to +70 c, C40 c to +85 c 3/5# pin set low for 5v operations temp comm extended sym parameter notes typ max typ max units test conditions i pps v pp standby/read 1 1 10 1 10 a v pp v cc i ppr current 65 200 65 200 a v pp > v cc i ppd v pp deep power- down current 1 0.2 5 0.2 5 a rp# = gnd 0.2v
e 28F016SA 31 see new design recommendations 5.5 dc characteristics: commercial and extended temperature (continued) v cc = 5.0v 10%, 5.0v 5%,t a = 0 c to +70 c, -40 c to +85 c 3/5# pin set low for 5v operations temp comm/extended sym parameter notes min typ max units test conditions i ppw v pp program current for word or byte 1 7 12 ma v pp = v pph program in progress i ppe v pp block erase current 1 5 10 ma v pp = v pph block erase in progress i ppes v pp erase suspend current 1 65 200 a v pp = v pph block erase suspended v il input low voltage C0.5 0.8 v v ih input high voltage 2.0 v cc +0.5 v v ol output low voltage 0.45 v v cc = v cc min i ol = 5.8 ma v oh1 output high voltage 0.85 v cc vv cc = v cc min i oh = C2.5 ma v oh2 v cc C0.4 vv cc = v cc min i oh = C100 a v ppl v pp during normal operations 3 0.0 6.5 v v pph v pp during program/ erase operations 11.4 12.0 12.6 v v lko v cc program/erase lock voltage 2.0 v notes: 1. all currents are in rms unless otherwise noted. typical values at v cc = 5.0v, v pp = 12.0v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. i cces is specified with the device deselected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. block erases, word/byte programs and lock block operations are inhibited when v pp = v ppl and not guaranteed in the range between v pph and v ppl . 4. automatic power saving (aps) reduces i ccr to less than 2 ma in static operation. 5. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 6. standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer. default the device into read array or read status register mode before entering standby to ensure standby current levels.
28F016SA e 32 see new design recommendations 5.6 ac characteristics Cread only operations: commercial and extended temperature (1) v cc = 3.3v 10%, t a = 0 c to +70 c, C40 c to +85 c temp commercial extended speed C120 C150 C150 sym parameter v cc 3.3v 10% units load 50 pf notes min max min max min max t avav read cycle time 120 150 150 ns t avqv address to output delay 120 150 150 ns t elqv ce# to output delay 2 120 150 150 ns t phqv rp# high to output delay 620 750 750 ns t glqv oe# to output delay 2 45 50 50 ns t elqx ce# to output in low z 3 0 0 0 ns t ehqz ce# to output in high z 3 30 35 35 ns t glqx oe# to output in low z 3 0 0 0 ns t ghqz oe# to output in high z 3 15 20 20 ns t oh output hold from address, ce# or oe# change, whichever occurs first 3000ns t flqv t fhqv byte# to output delay 3 120 150 150 ns t flqz byte# low to output in high z 3 304040ns t elfl t elfh ce# low to byte# high or low 3555ns for extended status register reads temp commercial extended speed C120 C150 symbol parameter v cc 3.3v 10% units load 50 pf notes min max min max t avel address setup to ce# going low 3,4 0 0 ns t avgl address setup to oe# going low 3,4 0 0 ns
e 28F016SA 33 see new design recommendations 5.6 ac characteristics Cread only operations: commercial and extended temperature (1) (continued) v cc = 5.0v 10%, 5.0v 5%, t a = 0 c to +70 c. C40 c to +85 c temp commercial comm/ext speed C70 C80 C100 sym parameter v cc 5.0v 5%v 5.0v 10%v 5.0v 10%v units load 30 pf 50 pf 50% notes min max min max min max t avav read cycle time 70 80 100 ns t avqv address to output delay 70 80 100 ns t elqv ce# to output delay 2 70 80 100 ns t phqv rp# to output delay 400 480 550 ns t glqv oe# to output delay 2 30 35 40 ns t elqx ce# to output in low z 3 0 0 0 ns t ehqz ce# to output in high z 3 25 30 30 ns t glqx oe# to output in low z 3 0 0 0 ns t ghqz oe# to output in high z 3 15 15 15 ns t oh output hold from address, ce# or oe# change, whichever occurs first 3000ns t flqv t fhqv byte# to output delay 3 70 80 100 ns t flqz byte# low to output in high z 3 253030ns t elfl t elfh ce# low to byte# high or low 3555ns
28F016SA e 34 see new design recommendations for extended status register reads temp commercial commercial comm/ext load 30 pf 50 pf 50 pf versions (5) v cc 5% 28F016SA-070 (6) units v cc 10% 28F016SA-080 (7) 28F016SA-100 (7) sym parameter notes min max min max min max t avel address setup to ce# going low 3,4 0 0 0 ns t avgl address setup to oe# going low 3,4 0 0 0 ns notes: 1. see ac input/output reference waveforms for timing measurements, figures 7 and 8. 2. oe# may be delayed up to t elqv Ct glqv after the falling edge of ce# without impact on t elqv . 3. sampled, not 100% tested. 4. this timing parameter is used to latch the correct bsr data onto the outputs. 5. device speeds are defined as: 70/80 ns at v cc = 5.0v equivalent to 120 ns at v cc = 3.3v 100 ns at v cc = 5.0v equivalent to 150 ns at v cc = 3.3v 6. see ac input/output reference waveforms and ac testing load circuits for high speed test configuration. 7. see standard ac input/output reference waveforms and ac testing load circuit.
e 28F016SA 35 see new design recommendations high z high z addresses stable valid output v ih v il v ih v il v ih v il v ih v cc gnd 5.0v v ih v il t t t t t phqv avqv glqv elqv t glqx t elqx t avav t ehqz t ghqz oh addresses (a) oe# (g) we# (w) data (d/q) rp# (p) v ol t avgl t avel cex# (e) (1) v il v oh 0489_11 note: 1. ce x # is defined as the latter of ce 0 # or ce 1 # going low or the first of ce 0 # or ce 1 # going high. figure 12. read timing waveforms
28F016SA e 36 see new design recommendations high z high z addresses stable v ih v il v ih v il v ih v il v ih v il v oh v ol t t t avqv glqv t elqv t glqx elqx avav t ehqz t ghqz t oh addresses (a) byte# (f) data (dq0-dq7) oe# (g) t avfl t elfl t flqv = t avqv data output = t elfl high z data output data output high z data (dq8-dq15) t flqz t avel t avgl v oh v ol t cex #(e) (1) 0489_12 note: 1. ce x # is defined as the latter of ce 0 # or ce 1 # going low or the first of ce 0 # or ce 1 # going high. figure 13. byte# timing waveforms
e 28F016SA 37 see new design recommendations 5.7 power-up and reset timings: commercial/extended temperature rp# 3/5# 0v 3.3v v power-up cc 5.0v v cc (p) (y) (3v,5v) 4.5v plyl t t pl5v ylph t yhph t valid 5.0v outputs valid valid address data valid 3.3v outputs avqv t (a) (q) avqv t phqv t phqv t phel3 t ce # phel5 t x 0489_13 figure 14. v cc power-up and rp# reset waveforms symbol parameter notes min max unit t plyl t plyh rp# low to 3/5# low (high) 0 s t ylph t yhph 3/5# low (high) to rp# high 1 2 s t pl5v t pl3v rp# low to v cc at 4.5v minimum (to v cc at 3.0v min or 3.6v max) 20 s t phel3 rp# high to ce# low (3.3v v cc ) 1 500 ns t phel5 rp# high to ce# low (5v v cc ) 1 330 ns t avqv address valid to data valid for v cc = 5v 10% 3 80 ns t phqv rp# high to data valid for v cc = 5v 10% 3 480 ns notes: ce 0 #, ce 1 # and oe# are switched low after power-up. 1. the t ylph /t yhph and t phel3 /t phel5 times must be strictly followed to guarantee all other read and program specifications. 2. the power supply may start to switch concurrently with rp# going low. 3. the address access time and rp# high to data valid time are shown for 5v v cc operation of the 28F016SA-080. refer to the ac characteristics read only operations for 3.3v v cc and all other speed options.
28F016SA e 38 see new design recommendations 5.8 ac characteristics for we# Ccontrolled command write operations: commercial and extended temperature (1) v cc = 3.3v 10%, t a = 0 c to +70 c, C40 c to +85 c temp commercial comm/extended sym parameter notes min typ max min typ max units t avav write cycle time 120 150 ns t vpwh v pp setup to we# going high 3 100 100 ns t phel rp# setup to ce# going low 480 480 ns t elwl ce# setup to we# going low 10 10 ns t avwh address setup to we# going high 2,6 75 75 ns t dvwh data setup to we# going high 2,6 75 75 ns t wlwh we# pulse width 75 75 ns t whdx data hold from we# high 2 10 10 ns t whax address hold from we# high 2 10 10 ns t wheh ce# hold from we# high 10 10 ns t whwl we# pulse width high 45 75 ns t ghwl read recovery before write 0 0 ns t whrl we# high to ry/by# going low 100 100 ns t rhpl rp# hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 ns t phwl rp# high recovery to we# going low 11s t whgl write recovery before read 95 120 ns t qvvl v pp hold from valid status register (csr, gsr, bsr) data and ry/by# high 00s t whqv1 duration of word/byte program operation 4,5 5 9 note 7 5 9 note 7 s t whqv2 duration of block erase operation 4 0.3 10 0.3 10 sec
e 28F016SA 39 see new design recommendations 5.8 ac characteristics for we# Ccontrolled command write operations: commercial and extended temperature (1) (continued) v cc = 5.0v 10%, 5.0v 5%, t a = 0 c to +70 c, C40 c to +85 c temp commercial commercial comm/ext versions v cc 5% 28F016SA-070 unit v cc 10% 28F016SA-080 28F016SA-100 sym parameter notes min typ max min typ max min typ max t avav write cycle time 70 80 100 ns t vpwh v pp setup to we# going high 3 100 100 100 ns t phel rp# setup to ce# going low 480 480 480 ns t elwl ce# setup to we# going low 000ns t avwh address setup to we# going high 2,6 50 50 50 ns t dvwh data setup to we# going high 2,6 50 50 50 ns t wlwh we# pulse width 40 50 50 ns t whdx data hold from we# high 20 0 0 ns t whax address hold from we# high 210 10 10 ns t wheh ce# hold from we# high 10 10 10 ns t whwl we# pulse width high 30 30 50 ns t ghwl read recovery before write 000ns
28F016SA e 40 see new design recommendations 5.8 ac characteristics for we# Ccontrolled command write operations: commercial and extended temperature (1) (continued) v cc = 5.0v 10%, 5.0v 5%, t a = 0 c to +70 c, C40 c to +85 c temp commercial commercial comm/ext versions v cc 5% 28F016SA-070 unit v cc 10% 28F016SA-080 28F016SA-100 sym parameter notes min typ max min typ max min typ max t whrl we# high to ry/by# going low 100 100 100 ns t rhpl rp# hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 0 ns t phwl rp# high recovery to we# going low 111 s t whgl write recovery before read 60 65 80 ns t qvvl v pp hold from valid status register (csr, gsr, bsr) data and ry/by# high 000s t whqv 1 duration of word/byte program operation 4,5 4.5 6 note 7 4.5 6 note 7 4.5 6 note 7 s t whqv 2 duration of block erase operation 4 0.3 10 0.3 10 0.3 10 sec
e 28F016SA 41 see new design recommendations notes: ce# is defined as the latter of ce 0 # or ce 1 # going low or the first of ce 0 # or ce 1 # going high. 1. read timings during data program and block erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, but not 100% tested. 4. data program/block erase durations are measured to valid status register data. 5. word/byte program operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of we# for all command write operations. 7. this information will be available in a technical paper. please call intels application hotline or your local intel sales office for more information. v v we# (w) oe# (g) rp# (p) v pp cex # (e) (v) deep power-down ih il v v ih il v v ih il addresses (a) t wheh elwl t t whdx whwl t v v ih il t wlwh t dvwh v ih il v v ih v il phwl t high z in dd in in a t t qvvl d in il v pph v in v t vpwh read extended status register data data (d/q) whqv1,2 write data-write or erase setup command write valid address & data (data-write) or erase confirm command automated data-write or erase delay v v ry/by# (r) t whrl t whgl oh ol v v ih il addresses (a) t avav avwh t t whax in a read compatible status register data d in write read extended register command a=ra note 1 note 2 note 3 note 4 d out t rhpl t ghwl note 5 ppl v t avav avwh t t whax 0489_14 notes: 1. this address string depicts data program/block erase cycles with corresponding verification via esrd. 2. this address string depicts data program/block erase cycles with corresponding verification via csrd. 3. this cycle is invalid when using csrd for verification during data program/block erase operations. 4. ce x # is defined as the latter of ce 0 # or ce 1 # going low or the first of ce 0 # or ce 1 # going high. 5. rp# low transition is only to show t rhpl ; not valid for above read and program cycles. figure 15. ac waveforms for command write operations
28F016SA e 42 see new design recommendations 5.9 ac characteristics for ce# Ccontrolled command write operations: commercial and extended temperature (1) v cc = 3.3v 10%, t a = 0 c to +70 c, -40 c to +85 c temp commercial comm/ext sym parameter speed -120 -150 unit notes min typ max min typ max t avav write cycle time 120 150 ns t vpeh v pp setup to ce# going high 3 100 100 ns t phwl rp# setup to we# going low 480 480 ns t wlel we# setup to ce# going low 0 0 ns t aveh address setup to ce# going high 2,6 75 75 ns t dveh data setup to ce# going high 2,6 75 75 ns t eleh ce# pulse width 75 75 ns t ehdx data hold from ce# high 2 10 10 ns t ehax address hold from ce# high 2 10 10 ns t ehwh we hold from ce# high 10 10 ns t ehel ce# pulse width high 45 75 ns t ghel read recovery before write 0 0 ns t ehrl ce# high to ry/by# going low 100 100 ns t rhpl rp# hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 ns t phel rp# high recovery to ce# going low 11s t ehgl write recovery before read 95 120 ns t qvvl v pp hold from valid status register (csr, gsr, bsr) data and ry/by# high 00s t ehqv1 duration of word/byte program operation 4,5 5 9 note 7 5 9 note 7 s t ehqv2 duration of block erase operation 4 0.3 10 0.3 10 sec
e 28F016SA 43 see new design recommendations 5.9 ac characteristics for ce# Ccontrolled command write operations: commercial and extended temperature (1) (continued) v cc = 5.0 to 10% , 5.0 5%, t a = 0c to +70 c, C40c to +85 c temp commercial commercial comm/ext versions v cc 5% 28F016SA-070 unit v cc 10% 28F016SA-080 28F016SA-100 sym parameter notes min typ max min typ max min typ max t avav write cycle time 70 80 100 ns t vpeh v pp setup to ce# going high 3 100 100 100 ns t phwl rp# setup to we# going low 3 480 480 480 ns t wlel we# setup to ce# going low 000ns t aveh address setup to ce# going high 2,6 50 50 50 ns t dveh data setup to ce# going high 2,6 50 50 50 ns t eleh ce# pulse width 40 50 50 ns t ehdx data hold from ce# high 20 0 0 ns t ehax address hold from ce# high 210 10 10 ns t ehwh we# hold from ce# high 10 10 10 ns t ehel ce# pulse width high 30 30 50 ns t ghel read recovery before write 000ns t ehrl ce# high to ry/by# going low 100 100 100 ns
28F016SA e 44 see new design recommendations 5.9 ac characteristics for ce# Ccontrolled command write operations: commercial and extended temperature (1) (continued) v cc = 5.0 to 10%, 5.0v 5%, t a = 0 c to +70 c, C40 c to +85 c temp commercial commercial comm/ext versions v cc 5% 28F016SA-070 unit v cc 10% 28F016SA-080 28F016SA-100 sym parameter notes min typ max min typ max min typ max t rhpl rp# hold from valid status register (csr, gsr, bsr) data and ry/by# high 30 0 0 ns t phel rp# high recovery to ce# going low 111 s t ehgl write recovery before read 60 65 80 s t qvvl v pp hold from valid status register (csr, gsr, bsr) data and ry/by# high 000s t ehqv1 duration of word/byte program operation 4,5 4.5 6 note 7 4.5 6 note 7 4.5 6 note 7 s t ehqv2 duration of block erase operation 4 0.3 10 0.3 10 0.3 10 sec notes: ce# is defined as the latter of ce 0 # or ce 1 # going low or the first of ce 0 # or ce 1 # going high. 1. read timings during data program and block erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, but not 100% tested. 4. data program/block erase durations are measured to valid status register data. 5. word/byte program operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of ce# for all command write operations. 7. this information will be available in a technical paper. pl ease call intels application hotline or your local intel sales office for more information.
e 28F016SA 45 see new design recommendations v v we# (w) oe# (g) rp# (p) v pp cex#(e) (v) deep power-down ih il v v ih il v v ih il addresses (a) t avav t ehax t ehwh wlel t t ehdx ehel t v v ih il t eleh t dveh v ih il v v ih v il phel t high z in d d in in a t qvvl d in il v ih v pph v ppl v t vpeh read extended status register data data (d/q) t ehqv1,2 write data-write or erase setup command write valid address & data (data-write) or erase confirm command automated data-write or erase delay v v ry/by# (r) t ehrl oh ol v v ih il addresses (a) in a read compatible status register data d in write read extended register command a=ra note 1 note 2 note 3 note 4 d out aveh t t rhpl t ghel note 5 t avav t ehax aveh t t ehgl 0489_15 notes: 1. this address string depicts data program/block erase cycles with corresponding verification via esrd. 2. this address string depicts data program/block erase cycles with corresponding verification via csrd. 3. this cycle is invalid when using csrd for verification during data program/block erase operations. 4. ce x # is defined as the latter of ce 0 # or ce 1 # going low or the first of ce 0 # or ce 1 # going high. 5. rp# low transition is only to show t rhpl ; not valid for above read and program cycles. figure 16. alternate ac waveforms for command write operations
28F016SA e 46 see new design recommendations 5.10 ac characteristics for page buffer write operations: commercial and extended temperature (1) v cc = 3.3v 10%, t a = 0 c to +70 c, C40 c to +85 c temp commercial comm/ext sym parameter speed C120 C150 unit notes min typ max min typ max t avav write cycle time 120 150 ns t elwl ce# setup to we# going low 10 10 ns t avwl address setup to we# going low 3 0 0 ns t dvwh data setup to we# going high 2 75 75 ns t wlwh we# pulse width 75 75 ns t whdx data hold from we# high 2 10 10 ns t whax address hold from we# high 2 10 10 ns t wheh ce# hold from we# high 10 10 ns t whwl we# pulse width high 45 75 ns t ghwl read recovery before write 0 0 ns t whgl write recovery before read 95 120 ns
e 28F016SA 47 see new design recommendations 5.10 ac characteristics for page buffer write operations: commercial and extended temperature (1) (continued) v cc = 5.0v 10%, 5.0v 5%, t a = 0 c to +70 c, C40 c to +85 c temp commercial commercial comm/ext sym parameter speed C70 C80 C100 unit v cc 5.0v 5% 5.0v 10% 5.0v 10% notes min typ max min typ max min typ max t avav write cycle time 70 80 100 ns t elwl ce# setup to we# going low 000ns t avwl address setup to we# going low 3000ns t dvwh data setup to we# going high 2505050ns t wlwh we# pulse width 40 50 50 ns t whdx data hold from we# high 2000ns t whax address hold from we# high 2101010ns t wheh ce# hold from we# high 10 10 10 ns t whwl we# pulse width high 30 30 50 ns t ghwl read recovery before write 000ns t whgl write recovery before read 60 65 80 ns notes: ce# is defined as the latter of ce 0 # or ce 1 # going low or the first of ce 0 # or ce 1 # going high. 1. these are we# Ccontrolled write timings, equivalent ce#Ccontrolled write timings apply. 2. sampled, but not 100% tested. 3. address must be valid during the entire we# low pulse or the entire ce# low pulse for ce#-controlled writes.
28F016SA e 48 see new design recommendations we# (w) cex#(e) v v ih il elwl t t whdx v v ih il t wlwh t dvwh v ih il v high z in d data (d/q) v v ih il addresses (a) t whax valid t avwl t wheh t whwl 0489_16 figure 17. page buffer write timing waveforms (loading data to the page buffer)
e 28F016SA 49 see new design recommendations 5.11 erase and word/byte write performance, cycling performance and suspend latency (3) v cc = 3.3v 10% , v pp = 12.0v 0.6v, t a = 0 c to +70 c sym parameter notes min typ (1) max units test conditions page buffer byte write time 2,4 3.26 note 6 s page buffer word write time 2,4 6.53 note 6 s t whrh 1 word/byte program time 2 9 note 6 s t whrh 2 block program time 2 0.6 2.1 sec byte prog. mode t whrh 3 block program time 2 0.3 1.0 sec word prog. mode block erase time 2 0.8 10 sec full chip erase time 2 25.6 sec erase suspend latency time to read 7.0 s auto erase suspend latency time to write 10.0 s erase cycles 5 100,000 1,000,000 cycles v cc = 5.0v 10%, v pp = 12.0v 0.6v, t a = 0 c to +70 c sym parameter notes min typ (1) max units test conditions page buffer byte write time 2,4 2.76 note 6 s page buffer word write time 2,4 5.51 note 6 s t whrh 1 word/byte program time 2 6 note 6 s t whrh 2 block program time 2 0.4 2.1 sec byte prog. mode t whrh 3 block program time 2 0.2 1.0 sec word prog. mode block erase time 2 0.6 10 sec full chip erase time 2 19.2 sec erase suspend latency time to read 5.0 s auto erase suspend latency time to write 8.0 s erase cycles 5 100,000 1,000,000 cycles notes: 1. +25 c, v cc = 3.3v or 5.0v nominal, v pp = 12.0v nominal, 10k cycles. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. this assumes using the full page buffer to data program to the flash memory (256 bytes or 128 words). 5. typical 1,000,000 cycle performance assumes the application uses block retirement techniques. 6. this information will be available in a technical paper. please call intels application hotline or your local intel sales office for more information.
28F016SA e 50 see new design recommendations 6.0 derating curves 290489-16.eps figure 18. i cc vs. frequency (v cc = 5.5v) for x8 or x16 operation 290489-18.eps figure 19. i cc during block erase 290489-19.eps figure 20. i cc vs. frequency (v cc = 3.6v) for x8 or x16 operation 290489-21.eps figure 21. i pp during block erase
e 28F016SA 51 see new design recommendations 290489-24.eps figure 22. access time (t acc ) vs. output loading 290489-25.eps figure 23. i pp during word write operation 290489-26 figure 24. i pp during page buffer write operation
28F016SA e 52 see new design recommendations 7.0 mechanical specifications for tsop 290489-28.eps figure 25. mechanical specifications of the 28F016SA 56-lead tsop type 1 package family: thin small outline package symbol millimeters minimum nominal maximum notes a 1.20 a 1 0.05 a 2 0.965 0.995 1.025 b 0.100 0.150 0.200 c 0.115 0.125 0.135 d 1 18.20 18.40 18.60 e 13.80 14.00 14.20 e 0.50 d 19.80 20.00 20.20 l 0.500 0.600 0.700 n56 ? 0 3 5 y 0.100 z 0.150 0.250 0.350
e 28F016SA 53 see new design recommendations 8.0 mechanical specifications for ssop e 1 y c a1 b e d see detail a detail a he a r2 a2 r1 l 1 b a 0528_20 figure 26. mechanical specifications of the 56-lead ssop package family: shrink small outline package symbol millimeters minimum nominal maximum notes a 1.80 1.90 a1 0.47 0.52 0.57 a2 1.18 1.28 1.38 b 0.25 0.30 0.40 c 0.13 0.15 0.20 d 23.40 23.70 24.00 e 13.10 13.30 13.50 e 1 0.80 he 15.70 16.00 16.30 n56 l 1 0.45 0.50 0.55 y 0.10 a 2 3 4 b335 r1 0.15 0.20 0.25 r2 0.15 0.20 0.25
28F016SA e 54 see new design recommendations 9.0 device nomenclature and ordering information da = commercial temperature 56-lead ssop e = commercial temperature 56-lead tsop t = extended temperature 56-lead ssop access speed a2 6 8 f 000 1sa - 7 70 ns 100 ns 100 ns d 0489_18 valid combinations option order code v cc = 3.3v 10%, 50 pf load v cc = 5.0v 10%, 100 pf load v cc = 5.0v 5%, 30 pf load 1 e28F016SA-070 e28F016SA-120 e28F016SA-080 e28F016SA-070 2 e28F016SA-100 e28F016SA-150 e28F016SA-100 3 da28F016SA-070 da28F016SA-120 da28F016SA-080 da28F016SA-070 4 da28F016SA-100 da28F016SA-150 da28F016SA-100 5 dt28F016SA-100 dt28F016SA-150 dt28F016SA-150 dt28F016SA-150
e 28F016SA 55 see new design recommendations 10.0 additional information order number document/tool 297372 16-mbit flash product family users manual 290608 word-wide flashfile? memory family 28f160s3, 28f320s3 datasheet 290609 word-wide flashfile? memory family 28f160s5, 28f320s5 datasheet 290598 byte-wide smart 3 flashfile? memory family datasheet 290597 byte-wide smart 5 flashfile? memory family datasheet 290429 28f008sa 8-mbit flashfile? memory datasheet 292126 ap-377 16-mbit flash product family software drivers 28F016SA, 28f016sv, 28f016xs, 28f016xd 292144 ap-393 28f016sv compatibility with 28F016SA 292159 ap-607 multi-site layout planning with intels flash file? components 297408 28F016SA/dd28f032sa specification update 297534 small and low-cost power supply solution for intels flash memory products (technical paper) 297508 flashbuilder design resource tool notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers shou ld contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

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